1. Field of Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device by a gate-last process.
2. Description of Prior Art
Semiconductor devices have continued to decrease in size. A polysilicon gate is typically used but impedes an improvement of properties of a metal oxide semiconductor (MOS) device, because it has an excessively high gate resistance, a polysilicon depletion effect, and a boron penetration effect in a PMOS transistor. Moreover, an integration of the polysilicon gate with a high K dielectric usually introduces a large amount of interface defects, which causes a threshold voltage pinning effect of the device and reduces carrier mobility in a channel. Therefore, a gate structure in which a polysilicon gate is replaced with a metal gate is proposed.
A process of integrating a metal gate/high K gate stack in a MOS device includes a gate-first process and a gate-last process. In the gate-first process, the metal gate/high K gate stacks are firstly formed, and dopant implantation and activation anneal steps are then performed in source/drain regions. In the step of activation anneal for the source/drain regions, most of the metal gates react with the high K gate dielectric. Hence, in the gate-first process, the materials of the metal gate are constrained, which in turn suppresses an improvement of the threshold voltage. However, in the gate-last process, a dummy gate (i.e. a sacrificial gate) of for example the polycrystalline silicon is firstly formed, and dopant implantation and activation anneal steps are then performed in source/drain regions. Finally, the dummy gate is removed and the metal gate (i.e. a replacement gate) is formed. In the gate-last process, the material of the metal gate does not undergo the step of activation anneal in the source/drain regions. A temperature of the process after the metal gate is formed is generally lower than 500° C. With the gate-last process, more kinds of materials can be used for the metal gate, so as to obtain a desired threshold voltage and to reduce defect density at an interface between the metal gate and high K. Therefore, the gate-last process has become an increasingly attractive choice for integration of the metal gate.
In the gate-last process, an Interlayer Dielectric (ILD) layer is required to cover the dummy gate after the dummy gate is formed. A planar surface of the ILD layer is formed by Chemical Mechanical Polishing (CMP). Then, the dummy gate is removed and an opening is formed due to the removal of the dummy gate. The opening is filled with the material of the metal gate.
Further, a metal wiring layer is separated from an active layer of the semiconductor device by the ILD layer. The electric connection between the metal wiring layer and the active layer of the semiconductor device can be implemented by means of conductive vias through the ILD layer. The ILD layer having the planar surface is beneficial for depositing and patterning the metal gate material, and also is beneficial for electrical isolation between the metal wiring layer and the underlying layer of the semiconductor device, and further is beneficial for forming multi-level metal wiring interconnections. The ILD layer having the planar surface also improves mechanical strength and reliability of the semiconductor device, because there is no defect such as holes.
However, compared with the gate-first process, the gate-last process includes an additional CMP process in order to provide the ILD layer having the planar surface, which increase complexity and costs of the gate-last process, especially for a first insulating layer for isolating the gate stack structure with a super small gate length.
The CMP process can be replaced with a dual-layer ILD layer structure provided by firstly depositing a conformal insulating layer, such as including a low temperature oxide (LTO) layer, and then depositing a spin-on glass (SOG) layer thereon, wherein the LTO layer forms a conformal layer which covers a large area of a wafer, and the SOG layer further fills recesses on the surface, and thus a substantially planar surface can be obtained.
Then, in order to further form a flatter planar surface, the SOG layer can be etched back by using dry etching method, such as reactive ion etching (RIE), so as to planarize its surface. Typically, a mixture of trifluoromethane (CHF3), tetrafluoromethane (CF4) and Oxygen (O2) is used as an etching gas in the RIE.
In U.S. Pat. No. 5,316,980A of Shinichi Takeshiro etc., it is further proposed that a mixture of trifluoromethane (CHF3) and hexafluoroethane (C2F6) can be used as the etching gas, so that an etching rate of the organic SOG layer is lower than that of an underlying SiO2 layer. Consequently, a planar surface of the structure can still be provided even in a case that the underlying SiO2 layer is partly exposed.
However, the SOG layer etching method mentioned above actually can not achieve global planarization. It has been found that the etching rate of the SOG layer at the center of the wafer is lower than that at the edge of the wafer. As will be described, the etched SOG layer has a convex etching profile. As a result, the edge of the wafer has to be discarded since the thickness of SOG layer at the edge can not achieve the desired flatness and should be discarded, which reduces an available area of the wafer for manufacturing the semiconductor device.